Unlocking HPC Performance with AMD Tools & GPUs

🚀 HPC Training – October 28–30, 2025

This three-half-day program is aimed at HPC scientists, researchers, and practitioners who want to port, optimize, and profile their codes on AMD systems.

Program highlights:

• Day 1 (Beginner): HIP and ROCm introduction, OpenMP offloading, profiling basics.
• Days 2–3 (Advanced): advanced HIP/OpenMP, GPU-aware MPI, performance portability frameworks, AMD profiling tools, latest utilities (trace decoder, advanced profilers).
• Each module includes hands-on exercises.

Audience: researchers and engineers from academia or industry with prior HPC experience.

Prerequisites: Linux command-line, HPC software stack familiarity, compiling/running codes on HPC systems.

📅 Date: October 28–30, 2025 (from 1pm to 5pm each day CET)

⚠️Mandatory registration here (or on the top right of this page –>)

📍Format: Online: remote participants will access AMD infrastructures via the AMD Accelerator Cloud.

👉 This training will equip participants with the skills to efficiently exploit AMD GPUs and CPUs for high-performance workloads.

Organized by AMD, NCC France (CC-FR) and Castiel2, within the EuroCC Project.

Meet the AMD Team experts:

Bob Robey is a Principal Member of Technical Staff in the Data Center GPU Software Solutions Group at AMD
and is the global training Lead for GPU software. He has an extensive background in modeling
compressible fluid dynamics with shock waves. He has led the Parallel Computing Summer Research Internship program at Los Alamos National Laboratory for seven years. He is also a co-author with Yuliana Zamora for book Parallel and High Performance Computing, Manning Publications. He has over thirty years of experience in parallel computing and a decade in GPU computing.

Giacomo Capodaglio is a Member of the Technical Staff at AMD, working on developing and delivering trainings on AMD GPU software. He has a PhD in Applied Mathematics from Texas Tech University and a Master’s in Energy Engineering from the University of Bologna (Italy). Prior to joining AMD, Giacomo was a Scientist at Los Alamos National Laboratory, working on numerical methods for the ocean and sea ice components of the Department of Energy’s climate model E3SM. Besides climate, Giacomo’s work includes urban flooding modeling, uncertainty quantification and probability density estimation, and numerical methods development for nonlocal problems.

Samuel Antão has over 10 years experience in optimisation and performance tuning for HPC applications and systems with focus on accelerators. His work spans hardware design with FPGAs, programming model research, compiler development and application optimisation. Samuel has participated in several cutting edge projects around HPC in Europe and in US, including CORAL, having spearheaded the GPU support for OpenMP in Clang/LLVM and helping numerous scientists and software developers to adopt the latest HPC technology and making the most out it. Samuel Antao is a Senior Member of Technical Staff with AMD and AMD lead to the LUMI Center of Excellence.

George Markomanolis is Principal Member of Technical Staff Software Development Engineer at AMD.
He helps with the AMD training, among supporting European HPC sites. He works on understanding and porting codes for AMD GPUs. In his current and previous role, he prepared and gave many trainings regarding HIP porting, HIP programming, benchmarking GPUs, and evaluating various programming models that can be used on AMD GPUs. His research interests are in applications porting on GPUs, benchmarking, performance evaluation/optimization of HPC applications on various technologies, and parallel I/O analysis on filesystems. He is co-developer and member of the IO500 committee. Before joining AMD, he has worked in various supercomputing centers. He obtained his MSc in Computational Science from the National and Kapodistrian University of Athens, Greece in 2008 and his Ph.D. in Computer Science from the Ecole Normale Superieure de Lyon, France in 2014.

Jose Noudohouenou is a Principal Software Engineer at AMD with emphasis on application porting, optimization, and projection. While he is the AMD Center of Excellence (CoE) lead for Adastra machine at the CINES HPC center in Montpellier (France), Jose is also AMD’s technical lead for various systems in Europe including an exascale one. Before joining AMD, Jose worked at Intel and was involved in various federal HPC projects. He received a Ph.D. from University of Paris-Saclay (Versailles, France) and worked at Exascale Computing Research Lab in France as a postdoctoral researcher focusing on HW/SW codesign issues and the problem of matching codelet equivalence. Jose’s research interest includes both HPC and AI, HW/SW codesign issues, application tuning, and performance prediction.

Agenda:

The training is organized in 3 half days (1 to 5 PM):
>> Day 1 – Tuesday, October 28th (beginner level):
1:00 – 1:30 APU programming model
1:30 – 1:45 hands on exercises
1:45 – 2:30 Intro to HIP and ROCm – porting code to HIP
2:30 – 2:45 hands on exercises
2:45 – 3:15 Break
3:15 – 4:00 Intro to OpenMP offloading
4:00 – 4:15 hands on exercises
4:15 – 5:00 Intro to Profiling
>> Day 2 – Wednesday, October 29th (advanced level):
1:00 – 1:45 Advanced HIP
1:45 – 2:00 hands on exercises
2:00 – 2:45 Advanced OpenMP
2:45 – 3:00 hands on exercises
3:00 – 3:30 Break
3:30 – 4:00 OpenMP and HIP interoperability
4:00 – 4:15 hands on exercises
4:15 – 4:45 Performance portability frameworks (Kokkos, Std Par and similar)
4:45 – 5:00 hands on exercises
>> Day 3 – Thursday, October 30th (advanced level):
1:00 – 1:45 GPU-aware MPI
1:45 – 2:00 hands on exercises
2:00 – 2:45 Detailed overview of AMD tools and HPC community tools
2:45 – 3:00 hands on exercises
3:00 – 3:30 Break
3:30 – 4:00 Advanced profiling with practical examples
4:00 – 4:15 hands on exercises
4:15 – 4:45 Overview of latest tools like trace decoder
4:45 – 5:00 wrap up and closing